1. Field Of The Invention
The present invention relates generally to decoders, and more particularly to decoders which are achieved using bifet technology.
2. Related Art
A decoder is a device having input and output lines. The decoder selects one of its output lines according to the combination of values present on its input lines. When selecting an output line, the decoder sets the output line to either a low voltage value or a high voltage value, depending on whether the output lines are high or low, respectively, when not selected by the decoder. As used herein, the terms "select" and "enable" are used interchangebly.
Decoders are often used as access controllers for memory devices. This is shown in FIG. 1, where a decoder 104 controls access to a memory device 108.
The decoder 104 has N input lines 102 and 2.sup.N output lines 106 (the output lines 106 are also called word/bit lines 106 when the decoder 104 is used as an access controller as shown in FIG. 1). The memory device 108 has 2.sup.N rows and W memory cells per row. A one-to-one correspondence exists between the 2.sup.N word/bit lines 106 and the 2.sup.N rows of the memory device 108.
Ordinarily, the decoder 104 maintains the word/bit lines 106 in an unenabled state. When it is desired to read from or write to a row 114 of the memory device 108, an address of the row 114 is placed on the input lines 102. In response to the address, the decoder 104 enables a word/bit line 116 which corresponds to the row 114. The decoder 104 maintains the other word/bit lines in the unenabled state. Once the word/bit line 116 is enabled, it is possible to either read from or write to the memory cells associated with the row 114 by means of data lines 110. A selection line 112 may be provided to select specific memory cells in the row 114 for reading and writing.
A conventional decoder 104' is shown in FIG. 2. The conventional decoder 104' contains first decoders 212, 214 and second decoders 202.
The first decoders 212, 214 each contain four input lines 216, 218 (which correspond to the input lines 102 in FIG. 1) and sixteen output lines 226, 228.
While only one second decoder 202 is shown in FIG. 2, in practice the conventional decoder 104' contains 256 second decoders 202. The second decoders 202 contain word/bit lines 224, which correspond to the word/bit lines 106 in FIG. 1.
The second decoder 202 contains only metal oxide semiconductor field effect transistors (MOSFET), and specifically negative field effect transistors (NFET) 208, 210 and positive field effect transistors (PFET) 204, 206. Circuits using metal oxide semiconductor NFETs and PFETs are often called complementary metal oxide semiconductors (CMOS).
The second decoder 202 has two input nodes 230, 232. The output lines 226, 228 are connected to the input nodes 230, 232, which are in turn connected to the gates of the NFETs 208, 210 and the PFETs 204, 206. Each of the second decoders 202 is connected to and receives input from a different combination of the output lines 226, 228.
In operation, an 8 bit address is divided into two 4 bit addresses. The two 4 bit addresses are applied to the first decoders 212, 214 on the input lines 216, 218. Normally, the first decoders 212, 214 maintain the output lines 226, 228 at a high voltage state, such that the output lines 226, 228 are not enabled. In response to the 4 bit addresses, the first decoders 212, 214 each cause one of their respective output lines 226, 228 to go to a low voltage state, such that the output lines 226, 228 in the low voltage state are enabled.
For any particular second decoder 202, if either or both of its input nodes 230, 232 (which are connected to the output lines 226, 228) are in a high voltage state, then either or both NFETs 208, 210 are conductive, and at least one of the PFETs 204, 206 is nonconductive. As a result, the word/bit line 224 is pulled down to a low voltage state, such that the word/bit line 224 is not enabled.
If the input nodes 230, 232 are both at a low voltage state, then the NFETs 208, 210 are nonconductive and the PFETs 204, 206 are conductive. As a result, the word/bit line 224 is pulled up to a high voltage state, such that the word/bit line 224 is enabled.
While representing a functional decoder 104, the conventional decoder 104' is flawed with respect to performance and density. Specifically, the conventional decoder 104' is relatively slow in operation because it uses only field effect transistors (FET) 204, 206, 208, 210. In general, FETs are relatively slower than other transistor types (such as bipolar). Also, the density of the conventional decoder 104' is relatively low because FETs are physically larger than other transistor types (such as bipolar) for the same driving capability.
Another conventional decoder 104" is shown in FIG. 3. The conventional decoder 104" contains the first decoders 212, 214. The structure and operation of the first decoders 212, 214 are as described above with reference to FIG. 2.
The conventional decoder 104" also contains second decoders 322. While only one second decoder 322 is shown in FIG. 3, in practice the conventional decoder 104" contains 256 second decoders 322. The second decoders 322 contain word/bit lines 314, which correspond to the word/bit lines 106 in FIG. 1.
The second decoder 322 contains only bipolar transistors 304, 306, 308. The second decoder 322 has two input nodes 324, 326. The output lines 226, 228 are connected to the input nodes 324, 326, which are in turn connected to the bases of the bipolar transistors 306, 308. Each of the second decoders 322 is connected to and receives input from a different combination of the output lines 226, 228.
In operation, an 8 bit address is divided into two 4 bit addresses. The two 4 bit addresses are applied to the first decoders 212, 214 on the input lines 216, 218. Normally, the first decoders 212, 214 maintain the output lines 226, 228 at a high voltage state, such that the output lines 226, 228 are not enabled. In response to the 4 bit addresses, the first decoders 212, 214 each cause one of their respective output lines 226, 228 to go to a low voltage state, such that the output lines 226, 228 in the low voltage state are enabled.
The bipolar transistors 306, 308 represent a NOR gate. The bipolar transistor 304 represents an emitter follower.
For any particular second decoder 322, if either or both of its input nodes 324, 326 are at a high voltage state, then at least one of the bipolar transistors 306, 308 is conductive. Consequently, the base of the bipolar transistor 304 is held at a low voltage state. As a result, the word/bit line 314 is pulled down to a low voltage state, such that the word/bit line 314 is not enabled.
If the input nodes 306, 308 are both at a low voltage state, then the bipolar transistors 306, 308 are nonconductive. Consequently, the base of the bipolar transistor 304 is pulled up to a high voltage state. As a result, the word/bit line 314 is pulled up to a high voltage state, such that the word/bit line 314 is enabled.
The conventional decoder 104" represents a functional decoder 104. Also, because it uses only bipolar transistors 304, 306, 308, the conventional decoder 104" solves the performance and density problems of the conventional decoder 104' since bipolar transistors are generally faster and physically smaller than FETs for the same driving capability.
However, the conventional decoder 104" is flawed with respect to power dissipation. As shown in FIG. 3, the second decoders 322 always draw a significant amount of current. For example, while in the nonenabled state, the second decoders 322 draw current (and dissipate power) through the bipolar transistors 306, 308. While in the enabled state, the second decoders 322 draw current (and dissipate power) through the bipolar transistor 304.
Therefore, a decoder is required which achieves high performance, high density, and minimal power dissipation.